Caratterizzazione di un nuovo ASIC discriminatore di ioni singoli sviluppato per applicazioni di terapia con particelle

This thesis project aims at carrying out characterization measurements on a new prototype of front-end electronics for the readout of silicon detectors of the LGAD type which is under development for beam monitoring for applications in Hadron-therapy with proton beams. The project was carried out in the medical physics group of the Istituto Nazionale di Fisica Nucleare (INFN) in Turin. The context of this thesis is in the MoVeIT (modeling and verification for ion beam treatment planning) project started at INFN in 2016, and aims at developing innovative treatment planning systems, integrating new biological models to consider the impact of different effects, such as target fragmentation, relative biological efficacy, and intra-tumor heterogeneity. This requires innovative devices for characterization and beam monitoring in radiobiological and clinical irradiation. In particular, the project investigates the use of thin Low Gain Avalanche Diodes (LGAD) type silicon detectors named Ultra-Fast Silicon Detectors (UFSD) read out by a custom front-end chip. The first prototype of the chip, named Asynchronous-logic-Based Analog Counter for Ultra-fast Silicon strips (ABACUS), gave promising results but needed improvements and bug fixes, hence the need for a second prototype, on which the work of this thesis is focused. The new chip is called NEW ABACUS and features a new design of the internal DACs and a modified voltage biasing to achieve a better uniformity of the channels. The requirements that this chip must have are an input charge range from 3 to 150 fC; a rate/channel up to 100 MHz; an accuracy of less than 1%, dictated by the clinical requirement. To simulate the proton signal in the laboratory and characterize the chip, there is an input to inject charge through voltage pulses through a 40 fC capacitance is provided. The chip consists of an amplification stage that amplifies the input pulse, followed by a discriminator in which, by varying the threshold voltage via a DAC, the signal output from the preamplifier can be reconstructed. The discriminator is followed by the drivers system which outputs the signals as differential signals, which are then read by an FPGA. In order to increase the input frequency, a feedback-reset circuit is implemented which resets the feedback capacitor to allow the next incoming pulse to be seen. A 500 fC input capacitance was mounted on one of the test boards used to increase the charge range and fully characterize the chip. For the characterization, the setup consists of a test-board, on which the chip is mounted, which is powered by a power supply; the test-board is then interfaced with two FPGAs: one to control the signals arriving at the test-board and the other to receive the signals leaving the chip; the FPGAs are then read out and controlled through management program designed with LabView; a pulser is used to simulate the charge at the chip input. The characterization process consisted in the following steps: adapting the test-board to the chip used here; designing the program in LabView to control the FPGAs; designing the program in LabView to control the internal DACs and checking their functionality. The results were analyzed using LabView and Root analysis software and are reported in the thesis. ​