Sviluppo di Elettronica Integrata per Detector Monolitici in tecnologia Q-well CMOS

Abstract This thesis is part of the ongoing studies for the upgrades of the Inner Track- ing System of the Alice experiment at CERN. ALICE is the LHC experiment devoted to the study of ultra-relativistic heavy-ion collisions. The experiment is now in the data taking phase. In 2017-2018 the LHC will be shut down for a major maintenance and it is foreseen to use this opportunity to introduce also important improvements in the ALICE experimental apparatus. One of this system considered for the upgrade is the Inner Tracking System or ITS, which is the closest detector to the interaction point. The use of a smaller beam-pipe will allow to introduce high granularity detectors closer to the interaction point, improving the ver- tex reconstruction and giving access to new physics channels that cannot be explored with the present set-up. The data rate capability of the system will also be increased from today's rate of 1 kHz to 50 kHz in order to improve the statistics on rare events. Monolithic silicon detectors are considered in order to reduce the ma- terial budget. Since they do not need a conductive bond like hybrid pixel detectors, it is possible to get thinner sensors thus improving the impact pa- rameter resolution. Several approaches exist in order to design a monolithic CMOS sensors. The Quadruple well technology provided by TowerJazz is regarded as a very promising candidate. This technology allows in fact to built complex pixels embedding both digital and analog circuits within the sensitive area. Furthermore, the feature size of 0.18 ?m already allows for dense digital design. The development of the new ITS will be a large international collabora- tion and it involves teams from several institutions including IN2P3, CERN and INFN. The purpose is to develop new generation of CMOS sensors suited to the ALICE requirements. Such devices will need many high performance blocks performing di?erent functions: ampli?cation, data compression, power regulation, data transmission. One of the key components of the CMOS sen- 3 sors is the data transmission link. Here, it is necessary to combine a high data throughput with a small power consumption. In this work the design of such a link has been addressed. The link is based on the LVDS protocol, which is a widely used industrial standard. The link should work at a transmission rate of up to 1Gbit/s This thesis is organized as follows: ˆ In Chapter 1 some basic concepts about the detectors principle of op- eration are reported together with a brief description of some types of silicon sensors: the hybrid pixel sensors, the silicon strip and the silicon drift detectors. Furthermore, a description of the general purpose de- tector ALICE and of its components is given, paying special attention on the features of the actual ITS and on its limitations which motivate the upgrade. ˆ In Chapter 2 the state of the art in the Monolithic Active Pixel Sensors is reported. We present the standards MAPS and its principle of oper- ation together with two alternative layout of the sensor: Deep N-well MAPS and INMAPS. Monolithic sensors based o charge collection by drift. ˆ Chapter 3 reports a description of the LVDS interface and of its speci- ?cations as well as the method used in order to analyze the quality of the transmitted signal, as the eye diagram. ˆ In Chapter 4 we describe the LVDS transceivers the we have designed. The circuit are implemented in the 0.18 ?m Q-well CMOS technology. Two transmitter desig