Collegamenti seriali ad alta velocità implementati su FPGA per il circuito di readout del MVD per l'esperimento PANDA

The PANDA (antiProton ANnihilation at DArmstadt) is one of the major project of the FAIR (Facility for Antiproton and Ion Research) complex of the G.S.I. located at Darmstadt (Frankfurt), and is expected to start its operation in 2019. The PANDA collaboration proposed to built a state-of-the-art universal detector at the High Energy Storage Ring (HESR), for strong interaction studies. The experiment will explore Quantum Chromo Dynamics (QCD) theory in the energy range between the perturbative and non-perburbative regime studying the interaction between antiprotons and fixed target. The INFN group of Turin is studying the front-end electronic for the Micro Vertex Detector (MVD), which is the detector closest to the interaction point. The VLSI group of Turin is developing the chip ToPix designed to process the signal coming from the pixel sensors. In this thesis is analyzed the need of the serial link implemented on FPGA for the transfer of the data from inside the detector to its outer part from where the information are sent to the control room. Chapter 1 of the thesis provides a concise introduction to the PANDA detector, while chapter two discussed some general aspects of the integrated electronics and the serial communication. In chapter 3 the programmable logic are described, in particular is discussed the architecture of the device used during this work. The characterization of a multi-gigabit transceiver and the design of a serializer is then treated in chapter 4 and 5.